Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Megacore IP with modelsim ?!?

Hi,

I'm trying to simulate my desgin project containing the "tripple speed ethernet IP" i cannot simulate it in quartus because the arria 2 gx is not supported by the quartus simulator. In order to simulate it over modelsim i'll get these messages while compiling the "EDA netlist":

Error: Can't generate netlist output files because the license for encrypted file "C:/altera/80/ip/triple_speed_ethernet/lib/altera_tse_crc32galois8.v" is not available

Is there any way to simulate it before purchasing the license for it ?

Thanks in advance

edit: found this:

Altera's free OpenCore Plus hardware evaluation feature allows you to perform the following actions with all Altera® IP cores and some partner IP cores:

  • simulate the core behavior within your system

  • Verify the design functionality and quickly evaluate its size and speed

  • Generate time-limited device programming files for designs that incorporate MegaCore functions or partner IP

  • Program a device and verify the design in hardware

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    Hi,

    first of all thanks for the reply.

    1. the "tripple speed ethernet IP" is custom made(not by me). It hasnt been generated by the megawizard plugin manager. Is there any way how i could generate a simulation model myself?

    2. Even when i would have a simulation model file for the "tripple speed ethernet IP" i could only run a RTL functional Simulation which is without timing characteristics(sdo/sdf-file)?!?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    i am not sure why a custom triple speed ethernet MAC would be using the encrypted Altera HDL, but looks like you'll still need an Altera TSE license to fully use the core.

    that's correct, you'd have to buy the core to do a gate level simulation, otherwise use timing analysis rather than a timing simulation.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    I am having the same problem, but I want to do (at least RTL-level) simulation with ModelSim, so disabling the tool isn't an option.

    I can reproduce this with the following steps with Quatrus 14.1 (Web or Subscription Edition):

    * Create a New Project

    * Add an instance of the Altera TSE MAC IP Core

    * Create a top level Verilog file that instantiates the core and has some output

    * Attempt to build

    The build gets through all of the steps up to EDA Netlist Writer and then fails with:

    Info: Running Quartus II 64-Bit EDA Netlist Writer

    Info: Version 14.1.0 Build 186 12/03/2014 SJ Web Edition

    Info: Processing started: Wed Mar 11 12:26:00 2015

    Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off test -c test

    Error (204009): Can't generate netlist output files because the license for encrypted file "/home/smcrae/altera-tmp/test/blah/altera_tse_mac_control.v" is not available

    Error (204009): Can't generate netlist output files because the license for encrypted file "/home/smcrae/altera-tmp/test/blah/altera_tse_altshifttaps.v" is not available

    All of documentation seems to indicate that both RTL and Gate level simulation of IP Cores is supported in evaluation without a license (i.e.

    https://www.altera.com/en_us/pdfs/literature/hb/qts/qts_qii53014.pdf). I do get encrypted IEEE Verilog files in my project linked in through the .sip file, but I still get these errors during build.

    Am I doing something wrong?

    Thanks.