Honored Contributor
Honored ContributorI am having the same problem, but I want to do (at least RTL-level) simulation with ModelSim, so disabling the tool isn't an option.
I can reproduce this with the following steps with Quatrus 14.1 (Web or Subscription Edition): * Create a New Project * Add an instance of the Altera TSE MAC IP Core * Create a top level Verilog file that instantiates the core and has some output * Attempt to build The build gets through all of the steps up to EDA Netlist Writer and then fails with: Info: Running Quartus II 64-Bit EDA Netlist Writer Info: Version 14.1.0 Build 186 12/03/2014 SJ Web Edition Info: Processing started: Wed Mar 11 12:26:00 2015 Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off test -c test Error (204009): Can't generate netlist output files because the license for encrypted file "/home/smcrae/altera-tmp/test/blah/altera_tse_mac_control.v" is not available Error (204009): Can't generate netlist output files because the license for encrypted file "/home/smcrae/altera-tmp/test/blah/altera_tse_altshifttaps.v" is not available All of documentation seems to indicate that both RTL and Gate level simulation of IP Cores is supported in evaluation without a license (i.e. https://www.altera.com/en_us/pdfs/literature/hb/qts/qts_qii53014.pdf). I do get encrypted IEEE Verilog files in my project linked in through the .sip file, but I still get these errors during build. Am I doing something wrong? Thanks.
