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Fuad1's avatar
Fuad1
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1 year ago

Maximum SPI clock (SCLK) rate of SPI Intel FPGA IP

In an Arria 10 SoC design, what is the maximum supported SPI clock rate/data rate of the Intel FPGA SPI IP for slave and master modes? Regards,
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KennyT_altera's avatar
KennyT_altera
Icon for Super Contributor rankSuper Contributor
1 year ago

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions