Fuad1
New Contributor
New ContributorMaximum SPI clock (SCLK) rate of SPI Intel FPGA IP
In an Arria 10 SoC design, what is the maximum supported SPI clock rate/data rate of the Intel FPGA SPI IP for slave and master modes? Regards,
Forum Discussion
Fuad1New Contributor
New ContributorDear Kenny,
What you provided is the data rates for the HPS SPI controller. Would you please provide the maximum supported SPI clock rate/data rate of the Intel FPGA SPI IP (Altera Avalon 4 wire serial) for slave and master modes? Thank you.
Regards,
FvM
Super Contributor
Super ContributorHi,
maximal master sclk rate is clk/2 (clock divider 2, 4, 8 ...). Maximal slave sclk rate is clk/3 if read the doc correctly.
maximal master sclk rate is clk/2 (clock divider 2, 4, 8 ...). Maximal slave sclk rate is clk/3 if read the doc correctly.
