Fuad1
New Contributor
New ContributorMaximum SPI clock (SCLK) rate of SPI Intel FPGA IP
In an Arria 10 SoC design, what is the maximum supported SPI clock rate/data rate of the Intel FPGA SPI IP for slave and master modes? Regards,
Forum Discussion
KennyT_altera
Super Contributor
Super ContributorWe used bit rate for the calculation, you can check the information here https://www.intel.com/content/www/us/en/docs/programmable/683711/22-3/features-of-the-spi-controller.html
Fuad1Dear Kenny,
What you provided is the data rates for the HPS SPI controller. Would you please provide the maximum supported SPI clock rate/data rate of the Intel FPGA SPI IP (Altera Avalon 4 wire serial) for slave and master modes? Thank you.
Regards,
FvMHi,
maximal master sclk rate is clk/2 (clock divider 2, 4, 8 ...). Maximal slave sclk rate is clk/3 if read the doc correctly.
