I worte a document about this:
http://www.alteraforum.com/forum/showthread.php?t=2158&highlight=recovery+removal TimeQuest automatically constrains this(assuming you haven't cut paths between the clock domains of the source and destination), but it is reported as recovery and removal.
It concerns me that the reset only feeds "a few registers". As you can see from the document, the asynchronous port is designed for reset entire clock domains, and I would strongly recommend using it as logic, i.e. if you're resetting a counter or something, then do it synchronously. There are two major reasons:
1) Timing analysis probably won't be what you want, since different designers want something do this. When you're resetting small chunks of logic as part of your design, do you need that reset to reach the next stage of registers within a clock cycle? Technically you might, or else they could go metastable. If so, then you're analyzing the registers in two different ways, as a synchronous element(normal clocking operation) and as a combinatorial element(signals come through the asynch reset to the next destination registers). It generally doesn't make sense.
2) You can't do much logic on the reset anyway. If it's anything besides a single net, then you could have glitches that reset the logic. For example, if it's an AND gate, and one input is driving high, and you synchronously turn that off while turning the other signal on, you could get a glitch and reset the logic.
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