MAX_DELAY Keyword in TimeQuest

If it is truly an asynchronous reset, then why would you try and constrain the delay from the input port to the register(s)? Normally this would be cut with a set_false_path constraint. If you can relate it to the latch clock of the register somehow, e.g. with a virtual launch clock, then you can use a set_max_delay constraint to constrain it (but then it wouldn't be a truly asynchronous reset). In the next Quartus II release, 8.1, there is a new set_net_delay command that should do what you want to do if you can wait until then.