Max 10 timing simulation using ModelSim-Altera

Hi.

Look for fiftyfivenm (ModelSim-Altera precompiled library for Max 10).

I've a similar trouble. When I use the fiftyfivenm library, the LE's are not recognized in ModelSim and the start simulation reports errors. I didn´t find other library.

If you get success, post here.

For newer chips, (Cyclone V and later) Altera doesn't recommend using Modelsim for timing. Modelsim is recommended for RTL simulation/verification only. I don't know if there are libraries available for Max 10 or not. Altera recommends Timequest for all timing analysis.

From the Quartus handbook:

Note: Gate-level timing simulation of an entire design can be slow and should be avoided. Gate-level

timing simulation is supported only for the Stratix IV and Cyclone IV device families. Use

TimeQuest static timing analysis rather than gate-level timing simulation.

--- Quote Start ---

Hi, I've been doing simulations for my project so far using ModelSim-Altera. But so far I've only done functional simulation. I wanted to move onto timing simulation, but I hit a snag. I'm not able to find the device libraries for the Max 10 FPGAs in the modelsim folder ( \altera\14.1\modelsim_ase\altera\vhdl ). Is there a way to do timing simulation without these? Can i find these somewhere online maybe and add them to do timing simulation? thank you!

--- Quote End ---

Did you contacted my Altera support for red carpet support?

--- Quote Start ---

Did you contacted my Altera support for red carpet support?

--- Quote End ---

What is red carpet support by the way?

--- Quote Start ---

For newer chips, (Cyclone V and later) Altera doesn't recommend using Modelsim for timing. Modelsim is recommended for RTL simulation/verification only. I don't know if there are libraries available for Max 10 or not. Altera recommends Timequest for all timing analysis.

From the Quartus handbook:

Note: Gate-level timing simulation of an entire design can be slow and should be avoided. Gate-level

timing simulation is supported only for the Stratix IV and Cyclone IV device families. Use

TimeQuest static timing analysis rather than gate-level timing simulation.

--- Quote End ---

There are reasons other than timing closure for running GLS. I have a code which works fine as RTL but fails on the chip. I need to figure out where the problem is and the best way to do it is run a few GLS testcases.

Well, you can run post-synthesis / final timing GLS. All you need are the Device Source files and libraries. For this, you will have to manually compile all the timing libraries and sources from the Tool using ModelSim and place it into its respective libraries (Defaults). If you compile all of them to the "work" library, the simulation will not find them and may fail. Check Altera documentation on compiling device libraries in ModelSim/VCS/NCSim.

The device gate-level sources are mostly kept at this location:

(Drive:)\intelFPGA_pro\17.1\quartus\eda\sim_lib

You will need to create the following libraries and compile the files into them.

[TH] VHDL [/TH]

[TH] Verilog

[/TH]

Folder name: Lpm

File to compile: <220model.vhd, 220pack.vhd>

Folder name: lpm_ver

File to compile: 220model.v

Folder name: Sgate

File to compile: <sgate.vhd, sgate_pack.vhd>

Folder name: sgate_ver

File to compile: sgate.v

Folder name: stratixiigx_hssi

File to compile: <stratixiigx_hssi_atoms.vhd,stratixiigx_hssi_component.vhd>

Folder name: stratixiigx_hssi_ver

File to compile: stratixiigx_hssi_atoms.v

Folder name: stratixiigx

File to compile:

<stratixiigx_atoms.vhd, stratixiigx_components.vhd>

Folder name: stratixiigx_ver

File: stratixiigx_atoms.v

Folder name: work

File to compile: design files that have the extension .vo and .vht

Folder name: work

File to compile: design files that have the extension .vo and .vt