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Altera_Forum
Honored Contributor
Honored ContributorMax 10 timing simulation using ModelSim-Altera
Hi, I've been doing simulations for my project so far using ModelSim-Altera. But so far I've only done functional simulation. I wanted to move onto timing simulation, but I hit a snag. I'm not able t...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- For newer chips, (Cyclone V and later) Altera doesn't recommend using Modelsim for timing. Modelsim is recommended for RTL simulation/verification only. I don't know if there are libraries available for Max 10 or not. Altera recommends Timequest for all timing analysis. From the Quartus handbook: Note: Gate-level timing simulation of an entire design can be slow and should be avoided. Gate-level timing simulation is supported only for the Stratix IV and Cyclone IV device families. Use TimeQuest static timing analysis rather than gate-level timing simulation. --- Quote End --- There are reasons other than timing closure for running GLS. I have a code which works fine as RTL but fails on the chip. I need to figure out where the problem is and the best way to do it is run a few GLS testcases.
