Honored Contributor
Honored ContributorWell, you can run post-synthesis / final timing GLS. All you need are the Device Source files and libraries. For this, you will have to manually compile all the timing libraries and sources from the Tool using ModelSim and place it into its respective libraries (Defaults). If you compile all of them to the "work" library, the simulation will not find them and may fail. Check Altera documentation on compiling device libraries in ModelSim/VCS/NCSim.
The device gate-level sources are mostly kept at this location: (Drive:)\intelFPGA_pro\17.1\quartus\eda\sim_lib You will need to create the following libraries and compile the files into them. [TH] VHDL [/TH] [TH] Verilog [/TH] Folder name: Lpm File to compile: <220model.vhd, 220pack.vhd> Folder name: lpm_ver File to compile: 220model.v Folder name: Sgate File to compile: <sgate.vhd, sgate_pack.vhd> Folder name: sgate_ver File to compile: sgate.v Folder name: stratixiigx_hssi File to compile: <stratixiigx_hssi_atoms.vhd,stratixiigx_hssi_component.vhd> Folder name: stratixiigx_hssi_ver File to compile: stratixiigx_hssi_atoms.v Folder name: stratixiigx File to compile: <stratixiigx_atoms.vhd, stratixiigx_components.vhd> Folder name: stratixiigx_ver File: stratixiigx_atoms.v Folder name: work File to compile: design files that have the extension .vo and .vht Folder name: work File to compile: design files that have the extension .vo and .vt
