RRomano001
Contributor
ContributorMAX 10 foolished by? WHY???
Simple Edge detector doesn't work, just pipeline of signal doesn't work.
monitor of incoming signals, output signals, routed output signals to two pin:
On one is stuck at 0, on the other sample S@1....
-- Interrupt request acknowledge management on edge
SEQIRQ_IFC: process(SYS_CLK, ResetIn_n)
begin
if(RESetIn_n = '0') then
Local_IRQ_sampler <= (others => '0');
Seq_IRQREQ <= '0'; -- No IRQ
else
if rising_edge(SYS_CLK) then
-- clock edge
-- IRQ Edge sampling
Local_IRQ_sampler(1) <= Local_IRQ_sampler(0);
Local_IRQ_sampler(0) <= ETH_IRQREQ; -- (Sample) Ethernet RX end of UPD packet irq accepted irq request <-- Ethernet RX end of UPD packet irq request
-- Flag management
-- if Local_IRQ_sampler(1) = '0' and Local_IRQ_sampler(0) = '1' then
-- Seq_IRQREQ <= '1'; -- request IRQ
-- else --if Local_IRQ_sampler(1) = '0' and Local_IRQ_sampler(0) = '0' then
Seq_IRQREQ <= Local_IRQ_sampler(0); --'0';
-- end if;
-- clock edge
end if; -- clock edge
end if; -- Reset run
end process;
Changed to simple pipeline, still output is not correct.
On top trace signal from this module, bottom trace from outside of module, routed to LA.
Middle is the ETH_IRQREQ sampled on this module.
Seq_irqreq is the entity pin.
On top entity pin is routed to two different pin by simple direct assignment.
Same signal routed to a uController pin, that pin is stuck at one.
Logic and pin routed to LA is stuck at 0, seems quartus leave logic unconnected and signals assigned to default status.
