MAX 10 foolished by? WHY???

Update:

Entity interface:

-- Interrupt
	ETH_IRQREQ			: in	Std_Logic := '0';				-- Ethernet RX end of UPD packet irq request
	ETH_IRQACK			: out	Std_Logic := '0';			-- Ethernet RX end of UPD packet irq accepted
	ETH_Status_Register 	: in Std_logic_Vector(7 downto 0) := (others => '0');	-- Status of transmitter/receiver
 
	SEQ_IRQREQ			: out	Std_Logic := '0';			-- Controller irq request

moved signal out of process to be mere combinatorial....

DMA_ACK		<= Local_DMA_ACK;
 
ETH_SEND		<= Local_ETHREG;
 
SEQ_IRQREQ	<= ETH_IRQREQ;			-- Controller irq request <-- Ethernet RX end of UPD packet irq request
 
 
--	Local_PWR_FLT	<= (others => '0');
--	Local_MODECFG	<= (others => '0');
 
	-- RD/WR Status flags
 
	SEQ_Debug(3 downto 0) <= Local_StatePrb;	-- state counter
	SEQ_Debug(4) <= Local_DMA_ACK;
--	SEQ_Debug(5) <= Local_DMA_IsRDing;
	SEQ_Debug(6) <= SPI_WR_READY;
	SEQ_Debug(7) <= SPI_RD_READY;
	SEQ_Debug(5) <= ETH_IRQREQ;
--	SEQ_Debug(6) <= '0';
--	SEQ_Debug(7) <= '0';
--------------------------------------------------------------------------
-- Entity - Signal connection End ----------------------------------------
--------------------------------------------------------------------------

Signals:

ETHIRQ on this module from debug signal. (Element 5 of vector)

ETH_IRQ on external generating module

SEQ_Irqreq outside this module.

Freezed project files to document this again fool issue.

LA pin is low, uController sample High, seems SEQ_IRQREQ disappeared from design and default signal take on place.

Edit:

Top module:

Entity:

-- ---  STM IO ---------------------------------
			TXDE1_ST			: inout Std_Logic  := 'Z';	--	Released to controller
			RX1_ST			: inout Std_Logic  := 'Z';	--	Released to controller
			TX1_ST			: inout Std_Logic  := 'Z';	--	Released to controller
			TXDE2_ST			: inout Std_Logic  := 'Z';	-- Active serial to Perihery
			RX2_ST			: inout Std_Logic  := 'Z';	-- Active serial to Perihery
			TX2_ST			: inout Std_Logic  := 'Z';	-- Active serial to Perihery
 
 
 			JTAGEN	: out Std_Logic;		-- User free I/O
 
........
 
 -- signals:
	signal	Local_irq_req				:	std_Logic	:= '0';	-- IRQ Request

connection:

Local_irq_req, is mapped to external module SEQ_IRQREQ interface.

TX1_ST		<=	Local_irq_req;
 
....
 
 
	JTAGEN	<= Local_irq_req; --Local_SPI_Debug_Port(20); --SPI_MOSI1;	-- LA 3 Local_Debug_PortW(3)