Forum Discussion

RRomano001's avatar
RRomano001
Icon for Contributor rankContributor
7 years ago

MAX 10 foolished by? WHY???

Simple Edge detector doesn't work, just pipeline of signal doesn't work. monitor of incoming signals, output signals, routed output signals to two pin: On one is stuck at 0, on the other sample S@...
RRomano001's avatar
RRomano001
Icon for Contributor rankContributor
7 years ago

changed pullup to pull down on microcontroller:

Confirm Pin is in default state 'Z'...

Pin state exported from module is in default state '0'.

Qsys or quartus or both?

changed order of code, cleaned project persist out.

Sorry don't ask inspect RTL, a bug on modelsim prevent from. I must hardwire some VHDL attribute 'high to do so. I cannot add subtle bug to my side.

RRomano001's avatar
RRomano001
Icon for Contributor rankContributor
7 years ago

Update:

Issue with interrupt gating never solved, I generated a workaround mapping unmasked interrupt signal to uController and managed it in software with some overhead till get solved.

Also reduced USART channel produce overhead to multiplexer, but this is the only solution I found about.

About pin found on HI Z, design stopped working on another core, so I realized the two USART interface where swapped by name on design.

After this both pin (LA and uController got driven low as expected.

Issue is still severe on internal at almost output pin driver still work same way on top level.