Mapping GTECH flops to Stratix III

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Hi All,

We are trying, as part of an ASIC Verification effort, to map Synopsys DesignWare components (DW_*) to Stratix III.

Synopsys provides a path called GTECH netlists for simulation and emulation but when we tried to Synthesis in Quartus II GTECH flops we got empty results as the GTECH flops are specified as tables/UDPs.

Has anybody successfully mapped GTECH netlist components to Stratix III?

Thanks.

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Only a question. Are you trying to map a netlist on the FPGA ?

If that is what we need to do, yes. We know that it is possible to use GTECH components on Emulators such as Veloce or Palladium.

The larger question is: aside from SynplifyPremier (which according to its literature can map DW_*) components, how else would you port ASIC code designed with DesignWare (DW_*) components to run on Stratix III?

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If that is what we need to do, yes. We know that it is possible to use GTECH components on Emulators such as Veloce or Palladium.

The larger question is: aside from SynplifyPremier (which according to its literature can map DW_*) components, how else would you port ASIC code designed with DesignWare (DW_*) components to run on Stratix III?

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Hi,

I looked a little bit in the Quartus documentation and I think there is no direct way to use DW elements in Quartus. As far as I know Synopsys itself stop all activities regarding FPGA synthesis, but they acquired the company Synplicity. Synplicity offers expensive tools (e.g SynplifyPro), but delivers very good synthesis results. I would assume that they support the DW directly. Maybe one of the tools could help you.

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Thanks pletz, it appears that SynplifyPremier can synthesize the DW_* components that I need directly without having to go through GTECH.

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Hi,

maybe I found a workaround for your problem, which runs without SynplifyPremier.

1. Generate a netlist of your designware elements with your ASIC synthesis tool.

2. Limit the number of Library cells to a minimum. Write a e.g. verilog description

for all used element. In case of arithmetic functions (e.g. adder) write a functional description, in order to make sure that the arithmetic resources of the FPGA could be used. This will reduce the Fmax decreasing by using a netlist to a minimum.

3. Add netlist and your "simple" Library to your Quartus project.

--- Quote Start ---

Hi,

maybe I found a workaround for your problem, which runs without SynplifyPremier.

1. Generate a netlist of your designware elements with your ASIC synthesis tool.

2. Limit the number of Library cells to a minimum. Write a e.g. verilog description

for all used element. In case of arithmetic functions (e.g. adder) write a functional description, in order to make sure that the arithmetic resources of the FPGA could be used. This will reduce the Fmax decreasing by using a netlist to a minimum.

3. Add netlist and your "simple" Library to your Quartus project.

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Hi pletz,

We explored several options, with different levels of translation down to converting UDPs of flops (what Quartus II 8.0SP1 has problems with) to real flops with the same behavior but our client preferred to keep it as close to the ASIC as possible, so we are going to go with SynplifyPro using a gtech.v library from the SynplifyPro installation directory that I had not used. In the past I was using a set of GTECH_*.v files from a Design Compiler directory.

After SynplifyPro generated .vqms using the SynplifyPro gtech.v we were able to correctly synthesize GTECH libraries with only a 30% combinational penalty vs. the original RTL for a non-DW component. Of course, DW_* components can only be synthesized with SynplifyPremier or with GTECH versions of the DW_* components.

Thanks for your input.