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Hi,
maybe I found a workaround for your problem, which runs without SynplifyPremier.
1. Generate a netlist of your designware elements with your ASIC synthesis tool.
2. Limit the number of Library cells to a minimum. Write a e.g. verilog description
for all used element. In case of arithmetic functions (e.g. adder) write a functional description, in order to make sure that the arithmetic resources of the FPGA could be used. This will reduce the Fmax decreasing by using a netlist to a minimum.
3. Add netlist and your "simple" Library to your Quartus project.
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Hi pletz,
We explored several options, with different levels of translation down to converting UDPs of flops (what Quartus II 8.0SP1 has problems with) to real flops with the same behavior but our client preferred to keep it as close to the ASIC as possible, so we are going to go with SynplifyPro using a gtech.v library from the SynplifyPro installation directory that I had not used. In the past I was using a set of GTECH_*.v files from a Design Compiler directory.
After SynplifyPro generated .vqms using the SynplifyPro gtech.v we were able to correctly synthesize GTECH libraries with only a 30% combinational penalty vs. the original RTL for a non-DW component. Of course, DW_* components can only be synthesized with SynplifyPremier or with GTECH versions of the DW_* components.
Thanks for your input.
Honored Contributor
