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Thanks pletz, it appears that SynplifyPremier can synthesize the DW_* components that I need directly without having to go through GTECH.
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Hi,
maybe I found a workaround for your problem, which runs without SynplifyPremier.
1. Generate a netlist of your designware elements with your ASIC synthesis tool.
2. Limit the number of Library cells to a minimum. Write a e.g. verilog description
for all used element. In case of arithmetic functions (e.g. adder) write a functional description, in order to make sure that the arithmetic resources of the FPGA could be used. This will reduce the Fmax decreasing by using a netlist to a minimum.
3. Add netlist and your "simple" Library to your Quartus project.
Honored Contributor
