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Altera_Forum's avatar
Altera_Forum
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17 years ago

Mapping GTECH flops to Stratix III

Hi All, We are trying, as part of an ASIC Verification effort, to map Synopsys DesignWare components (DW_*) to Stratix III. Synopsys provides a path called GTECH netlists for simulation a...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

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Hi All,

We are trying, as part of an ASIC Verification effort, to map Synopsys DesignWare components (DW_*) to Stratix III.

Synopsys provides a path called GTECH netlists for simulation and emulation but when we tried to Synthesis in Quartus II GTECH flops we got empty results as the GTECH flops are specified as tables/UDPs.

Has anybody successfully mapped GTECH netlist components to Stratix III?

Thanks.

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Only a question. Are you trying to map a netlist on the FPGA ?