You can use the Logic Lock feature in the Quartus in achieving specific placement and routing goals for your design. Logic Lock allows you to lock down the placement of certain logic elements (such as flip-flops, logic cells, or specific modules) to specific locations on the FPGA device.
Reference: https://www.intel.com/content/www/us/en/docs/programmable/683641/current/defining-regions.html
However, it's important to note that the excessive use of Logic Lock regions may limit the flexibility of the Quartus tool to place & route the logic and could potentially lead to decreased performance or congestion issues. Therefore, it is recommended to use Logic Lock judiciously and analyze the impact on the overall design.
Best Regards,
Richard Tan
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