Occasional Contributor
Super ContributorYou can use the Logic Lock feature in the Quartus in achieving specific placement and routing goals for your design. Logic Lock allows you to lock down the placement of certain logic elements (such as flip-flops, logic cells, or specific modules) to specific locations on the FPGA device.
Reference: https://www.intel.com/content/www/us/en/docs/programmable/683641/current/defining-regions.html
However, it's important to note that the excessive use of Logic Lock regions may limit the flexibility of the Quartus tool to place & route the logic and could potentially lead to decreased performance or congestion issues. Therefore, it is recommended to use Logic Lock judiciously and analyze the impact on the overall design.
Best Regards,
Richard Tan
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Occasional ContributorThanks for the reply. I am aware of Logic Lock region.
But I am asking about the fine-grain control over the routing. For example, with Logic Lock region, I don't have a control
over the nets that come in/out from the Logic Lock region. I want to control these nets so that they do not route over specific regions.
Super ContributorYou can set up routing regions that are associated with Logic Lock regions to do this. This is normally used in the partial reconfiguration design flow since it's like you are removing part of the design while it's running and the rest of the design can continue running. Look up routing regions and partial reconfiguration for details on this.
Occasional ContributorYes, I am aware of routing region as well. However, as mentioned in the reply above, the routing region does not have a control over the "interface nets." (the nets that come in/out from the logic lock region)
I want to control these nets so that they do not route over specific regions. My idea was to manually move over these nets if they end up routing over the regions. Thus, I asked the question whether we can manually route specific nets.
