Hello, I have following kind of input in my VHDL Program: type binary_array is array(0 to 1099) of std_LOGIC_VECTOR(13 downto 0); I run the Program successfully in Quratus and also tested it by giving such 1100 input via Testbench in Modelsim. But I am wondering how can I run that program on real FPGA board because number of input in real case is several thousands (not equal to 1099) which is not even fixed as input is given by means of antenna, receiver, Analog to digital converter, etc?? can anybody give some idea how can I manage the input? --Thanks in advance

My suggestion would be to consider using the in system memory content tool. You could add a VHDL/Verilog module to wrap around a RAM, and using this RAM to be your stimulus/response. -James

--- Quote Start --- Hello, But I am wondering how can I run that program on real FPGA board because number of input in real case is several thousands (not equal to 1099) which is not even fixed as input is given by means of antenna, receiver, Analog to digital converter, etc?? --- Quote End --- If your signal is from ADC then you process it as it comes. If you have to store it at some point then you can use memory defining how much storage is required. fpga pins are kept for ADC inputs. You don't have to compare an internal simulation stimulus with ADC in this way.

Hello, thanks for the reply first. --- Quote Start --- If your signal is from ADC then you process it as it comes. --- Quote End --- Yes, My signal is from ADC (daughter card: http://www.terasic.com.tw/cgi-bin/page/archive.pl?language=english&no=278) to FPGA pins. Does it mean that it repeat/reset automatically as soon as number of input reaches to maximum defined limit in the program (e.g. in my case 1099)? and it works even the input is more than 1099 samples? --- Quote Start --- If you have to store it at some point then you can use memory defining how much storage is required. --- Quote End --- Could you please provide a short description/example for this?

I take it you got some program inside your fpga that interfaces with your 0:1099 vector generator. Now you are happy with your program and want instead to get data from ADC then you connect 14 bits from ADC to your module instead of your vector generator. If ADC is not 14 bits then you resize it. That is assuming your program is meant to process ADC data directly. ADCs are various and you may need to do some reformatting if it is not giving you the right data format. Regarding start/reset then it is up to the way you are processing. If you are processing a continuous stream sample by sample then you don't need to think the same way as the case of block processing when you process a defined frame from start to end in which case you will need to store a frame while processing another. I can't give helpful examples without knowing what you want to do to inputs. It could be you want first to filter the data in a LPF then you do that nonstop. It could be then you do fft then you process it frame by frame and so on.

--- Quote Start --- I take it you got some program inside your fpga that interfaces with your 0:1099 vector generator. Now you are happy with your program and want instead to get data from ADC then you connect 14 bits from ADC to your module instead of your vector generator. If ADC is not 14 bits then you resize it. --- Quote End --- Yes, exactly. ADC is also 14 bits --- Quote Start --- That is assuming your program is meant to process ADC data directly. ADCs are various and you may need to do some reformatting if it is not giving you the right data format. --- Quote End --- The Daughter card uses ADC (AD 9248) whose output is either 2's complement or offset binary based on data format select pin (DFS) selected, as mentioned in its data Sheet. but I am still not sure which one is in my case as DFS selection is not clear to me from data sheet for channel A. It seems to me it is 2's complement output in channel A of ADC which I am using in my case. --- Quote Start --- Regarding start/reset then it is up to the way you are processing. --- Quote End --- I have to detect certain patterns of 5 pulses(every pulse have close to 25 samples) from the continuous streams of input coming from ADC and as soon as this pattern is detected I have to store the input data starting from that detected point. I have also attached the simulation here for clarification. Note: in this simulation, only 512 input is considered instead of 1099 I mentioned above.

Managing input on the FPGA board | Altera Community

14 Replies

Altera_Forum
Honored Contributor
13 years ago
--- Quote Start ---
remember rams can be dual ported, so you can add another address port to read to the PC.
--- Quote End ---

Sorry, I didn't understand it.

Info of SRAM I am using:
2MB (1Mx16) SRAM
SRAM_ADDR[19..0] i.e. 20 bit address port
SRAM_DQ[15..0] i.e. 16 bit data port

using Dual ported here means assign half of the address port to read to the PC and rest half for input of memory ?? or anything else?

and what is the meaning of read to PC? I mean by which interface to PC and in which format?
Altera_Forum
Honored Contributor
13 years ago
all the internal memory on the FPGA is dual ported. So the same memory hass access from two sepearte things. So there are 2x 20bit address port and 2x 16 bit data port (in the configuration you're talkingabout).

I suggest reading the altera cyclone guide (specifically the ram architecture) and the quartus HDL coding styles guide.
Altera_Forum
Honored Contributor
13 years ago
--- Quote Start ---
I suggest reading the altera cyclone guide (specifically the ram architecture)
--- Quote End ---

I found one here:
http://www.altera.com/support/examples/vhdl/vhd-true-dual-port-ram-sclk.html

Is it the right one what you have suggested?
Altera_Forum
Honored Contributor
13 years ago
That might help, but I was refering to the alter coding guidelines:
http://www.altera.com/literature/hb/qts/qts_qii51007.pdf

and the cyclone4 handbook, chapter on memory elements:
http://www.altera.com/literature/hb/cyclone-iv/cyiv-51003.pdf

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Managing input on the FPGA board

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