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Altera_Forum
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13 years ago

Managing input on the FPGA board

Hello, I have following kind of input in my VHDL Program: type binary_array is array(0 to 1099) of std_LOGIC_VECTOR(13 downto 0); I run the Program successfully in Quratus and also teste...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

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remember rams can be dual ported, so you can add another address port to read to the PC.

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Sorry, I didn't understand it.

Info of SRAM I am using:

2MB (1Mx16) SRAM

SRAM_ADDR[19..0] i.e. 20 bit address port

SRAM_DQ[15..0] i.e. 16 bit data port

using Dual ported here means assign half of the address port to read to the PC and rest half for input of memory ?? or anything else?

and what is the meaning of read to PC? I mean by which interface to PC and in which format?