Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Managing input on the FPGA board

Hello, I have following kind of input in my VHDL Program: type binary_array is array(0 to 1099) of std_LOGIC_VECTOR(13 downto 0); I run the Program successfully in Quratus and also teste...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

all the internal memory on the FPGA is dual ported. So the same memory hass access from two sepearte things. So there are 2x 20bit address port and 2x 16 bit data port (in the configuration you're talkingabout).

I suggest reading the altera cyclone guide (specifically the ram architecture) and the quartus HDL coding styles guide.