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AAnch's avatar
AAnch
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8 years ago

malloc selects Flash address for DMA transfers in memtest.c instead of SRAM

Hi, In the current design there is NIOSII, DMA, Flash & SRAM implemented targeted for Max 10 FPGA. Trying to perform the DMA transfer as per the reference memtest.c I see the below code in questi...
AAnch's avatar
AAnch
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7 years ago

Hi,

I am not using the SGDMA or SDRAM. Using the normal DMA controller IP.

Please find attached the system built snapshot. It must contain NIOSII processor, DMA Controller, Onchip memory (SRAM), Onchip Flash IP (intended for Max10 FPGA platform).

Try to run the memtest.c with the DMA enabled in test with below define enabled in the test. Intention is to perform a DMA transfer in this system. Source address (data_written) and destination address (data_read) must be within the SRAM region.

#define DMA_NAME