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Altera_Forum's avatar
Altera_Forum
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16 years ago

LVDS transmitter maximum output clock

Hello. I don't understand this (datasheet Stratix II GX, volume 2 10-17)

"The ANSI/TIA/EIA-644 standard specifies LVDS transmitters and receivers capable of operating at recommended maximum data signaling rates of 655 megabit per second (Mbps). However, devices can operate at slower speeds if needed, and there is a theoretical maximum of 1.923 gbps. Stratix II and Stratix II GX devices are capable of running at a maximum data rate of 1 gbps and still meet the ANSI/TIA/EIA-644 standard."

I want to operate at maximum speed outclock whit divide factor 1. So my outclock frequency is the same of output_data_rate. Megawizard maximum output clock is 717mhz.

Can I work at greater frequency? How?

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    717 MHz is the maximum output clock frequency for LVDS pins, so you can't achieve a higher data rate with divide factor of 1. A Clock frequency of 717 MHz involves a double toggle rate compared to a data rate of 717 Mbps. You must use a least a divide factor of two to achieve the maximum Stratix II GX LVDS data rate of 1040 Mbps.