Forum Discussion
Altera_Forum
Honored Contributor
16 years ago717 MHz is the maximum output clock frequency for LVDS pins, so you can't achieve a higher data rate with divide factor of 1. A Clock frequency of 717 MHz involves a double toggle rate compared to a data rate of 717 Mbps. You must use a least a divide factor of two to achieve the maximum Stratix II GX LVDS data rate of 1040 Mbps.