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marcorig
New Contributor
New ContributorLPM DIVIDE behaves differently between simulation and implementation
I have implemented a divider in a custom VHDL module in order to replace the instances of the LPM_DIVIDE IPs in my project. I've then checked the functionality of my module against the LPM_DIVIDE and...
jackiNew Contributor
New ContributorHi,
The LPM DIVIDE function in Intel FPGAs may behave differently between simulation and implementation due to synthesis optimizations, timing differences, and hardware constraints. Simulation tools often assume ideal conditions, while actual FPGA hardware introduces latency and resource limitations. The division operation might be pipelined in implementation, causing additional clock cycle delays. Mismatches in reset handling or clock domains can also lead to unexpected results. To ensure consistency, verify timing constraints, pipeline settings, and resource utilization in Intel Quartus Prime. Running post-implementation simulations can help detect and resolve discrepancies.
