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marcorig's avatar
marcorig
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9 months ago

LPM DIVIDE behaves differently between simulation and implementation

I have implemented a divider in a custom VHDL module in order to replace the instances of the LPM_DIVIDE IPs in my project. I've then checked the functionality of my module against the LPM_DIVIDE and...
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ShengN_altera's avatar
ShengN_altera
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9 months ago

Hi,


Understood that. Please let me know whether simple one only with the divider and an operands generator inside got same simulation and signal tap?


Thanks,

Regards,

Sheng


  • marcorig's avatar
    marcorig
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    9 months ago

    Hi Sheng,

    I've implemented this simple selfchecking module, which instantiates only the LPM_DIVIDE, stimulated with 1000 couple of operands. I've simulated the module, synthesized and checked its behavior with SignalTap. As I though, the strange behaviour previously observed is present also in this version:

    Considering the first operation:

    Operands:

    Numerator = FFFFFFEC82000000h = -83718307840d

    Denominator = 000000000Bh = 11d.

    The result is -83718307840/11 = -7610755258.181818 or -7610755258 with a remainder of -2, that are the outputs provided by the module during the simulation: Quotient: FFFFFFFE3A5D1746h and Remainder: 7FFFFFFFFEh

    On the other side, the implemented divider publishes these results:

    Quotient: FFFFFFFE3A5D1745h and remainder of 0000000009h, which are different from the one seen during simulation.

    I've tested the module using Quartus Prime Version 20.1.1 Build 720 11/11/2020 Patches 1.02std SJ Standard Edition implementing it on a Arria 10 10AX066K4F35I3SG.