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JBorr6's avatar
JBorr6
Icon for New Contributor rankNew Contributor
6 years ago
Solved

Loop unrolling doesn't improve the processing time of radix-4 butterfly

I am running an emulation of an FFT using aocl 19.1.0.240 with s10_gh1e1_4Dx2 board. But when I tried comparing the radix-4 butterfly with (#pragma unroll before the for loop) and without loop unrol...
EBERLAZARE_I_Intel's avatar
EBERLAZARE_I_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago

Hi,

I am unsure what the causes might be, we do have a tutorial on usage of loop unroll below:

https://software.intel.com/content/www/us/en/develop/documentation/oneapi-fpga-optimization-guide/top/fpga-optimization-flags-attributes-pragmas-and-extensions/loop-directives/unroll-pragma.html

https://github.com/intel/BaseKit-code-samples/blob/master/FPGATutorials/FPGAExtensions/LoopAttributes/loop_unroll/README.md

You could try the example, and if the problem persists let me know.