Honored ContributorHello.
I have a path in my project that does not meet timing constraints due to long ic delay. In chip planner it looks like |cell|->...->|cell|->|cell|-long delay->|i/o cell| so i want to align the path with the final io cell. How can I place the whole path into the LogicLock region without defining each node of this path?
Honored ContributorFind the entity in the tree on the left panel in Quartus and create a LogicLock region. But this is not what You want to do for better timing results. Add design constrains for this problem to solve.
Honored ContributorThere once were path-based groups for LogicLock, but they were removed because they were never used. (They were most useful in the days of Apex, when there was a clear "bin" size that you wanted your logic to fit into).
Assuming there's a timing constraint, then the fitter is trying to put it closer but can't. My guess is that there is something else pulling it in another direction. It might be a fanout to another I/O that is on the other side of the die, or maybe something pulling the source register far away. I would spend some time in TimeQuest trying to analyze why this is occuring. Usually forcing the fitter on what seems like a trivial path like this will fix this problem but break the other paths it is trying to balance. (Of course, there are times where this just works...)
