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Altera_Forum's avatar
Altera_Forum
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13 years ago

LogicLock question

Hello. I have a path in my project that does not meet timing constraints due to long ic delay. In chip planner it looks like |cell|->...->|cell|->|cell|-long delay->|i/o cell| so i want to align t...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Find the entity in the tree on the left panel in Quartus and create a LogicLock region. But this is not what You want to do for better timing results. Add design constrains for this problem to solve.