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Altera_Forum's avatar
Altera_Forum
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17 years ago

location assignment

Hi

I'm possibly trying to do something very unrecommended, but unusual situations require unusual methods.

I'd like to specify what CLKCTRL a certain signal shoud use - or at least from what block.

I tried that first with a LogicLock region, what had the result, that the CLKCTRLs in this region weren't used at all, even if the signal was a member of it.

I then tried to use set_location_assignment, what is completely ignored (not even a info about this). According to the quartus II handbook, using location assignments for CLKCTRL is not perfectly valid either.

Is there a way to force a signal onto a specific CLKCTRL?

thanks

emanuel

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    A complaint of mine too, in that it's so difficult to do this correctly. Anyway, from some code I have, there is a line like so:

    set_location_assignment CLKCTRL_G4 -to "toplevel|...:sii_clkctrl:clkctrl"

    I took out the middle of the hierarchy, since it's someone else's IP, but hopefully that points you in the right direction. I assume you're explicitly instantiating the altclkctrl block, which allows you to name it and therefore control thename to tag the assignment too.

    Another idea, although not positive if it will work, is to make a copy of your fit project and then back-annotate it to the routing level. Look in the .qsf for similar assignments and then cut-and-paste them into your design. Not sure if that will work.
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Thanks for the answer.

    I just realised that it indeed works with set_location_assignment - but not with wildcards.

    I cannot specify the blocks with altclkctrl, as the design is actually for an ASIC, the FPGA is only prototyping platform. And then comes the naming problem, what makes wildcards very useful for filtering changes in the name due to optimization. I can still uniquely specify which signal I need...

    Guess I should put some constraints to fix the name...
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    I don't look at it too closely, but would be surprised if the name really changed from compile to compile. I thought it would be based on the signal driving it, whcih would be pretty constant.

    Also, just because it's an ASIC doesn't mean you can't instantiate and ALTCLKCTRL and then bypass it in the other mode. One thing you could try is instantiate a function(my_altclkctrl or something) and when targeting the FPGA, read in the megafunction you created for this block, and for the ASIC read in a logic that just passes the signal through. There are all sorts of ways, which I'm sure you know more than me, that should accomplish this.
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Well, normally the names stay the same, that's correct. I had changes though, and they are a nasty surprise normally, because you don't expect them and then spend time looking for them...

    Actually I realised how to make the difference in the moment I got the mail that you replied ;)

    Took me kind of long to get this idea...

    Thanks for the help!

    /emanuel