New Contributor
New Contributor17.1 compiles this and it fits, easily. But during the compilation I see a message that I don't see with v. 20.1:
Warning (276020): Inferred RAM node "uart_wishbone:uart0|uart_core:uart|uart_send:transmitter|bram_fifo:tx_fifo|block_ram:fifo_ram|simple_dual_port_ram:dualp_ram|gen.mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
I sure like the part where it says, "Inferred RAM node...
Do I have to go back to 17.1?
Super ContributorYou described a set of registers in a Verilog Design File (.v) or VHDL Design File (.vhd) that behave as RAM. Analysis & Synthesis then replaces the registers with a RAM node that will later infer an instance of the altsyncram megafunction to implement the functionality of the registers using the memory blocks in the target device.
For further information related to this error, you can refer to this link:
https://www.intel.com/content/www/us/en/programmable/quartushelp/current/index.htm#msgs/msgs/winfer_ram_pass_through_logic_inserted_altsyncram.htm
New ContributorI think the lite version was dumbed down maybe to incentivise people to upgrade to pro version of the software. Or, I think there is a bug here.
I found it easiest just to stay with version 17.x which continues to handle this situation as I want.
