New Contributor
New ContributorI was precisely wondering about the program block.
So you have the proper workaround it seems :-)
Just out of curiosity : what was your motivation for using a program block ?
I have been teaching SV for as long as it exists and we even removed the chapter about the program block...
I remember that it was (in the early days of SV at least) a source of trouble in the SV scheduler implementation (and a source of non determinism across tools).
New ContributorThank you:)
I am beginner for learning SV for verification. In my Textbook it introduces the Program block that it is used to seperate the software block(Input stimulus written in Program) and hardware block(DUT).
Is that out of date?
New ContributorIn your case, it prevents you from using affordable versions of Questa, so it's definitely a serious reason to avoid the program block.
I could change my mind, but only the day I will see a clear advantage of using it.
Regular ContributorHello WFH,
Do you still see license issue on Questa? If you using free edition of Questa, should be not the license issue, but the limitation of the free version of Questa.
regards,
farabi
New ContributorThank you Farabi,
Yes, it looks like the limitation of the free version of Questa as you mentioned. When I abandoned the Program block, the TB works. Thank you for your pointing that out.:)
New ContributorIt seems there is a consensus confirming my statement about not using the SystemVerilog program block. (You should be careful about your textbook).
That's what AI answers to "is it a good idea to use the program block in systemverilog ?" :
In modern SystemVerilog verification, the short answer is no, it is generally no longer considered a good idea to use the program block. While it was introduced early on to solve a major problem, evolution in verification methodologies—specifically the widespread adoption of the Universal Verification Methodology (UVM) and the strategic use of Clocking Blocks—has made the program block largely redundant and, in many cases, a source of subtle bugs.
New ContributorYes, It seems that my textbook teaches only about the old basic usage of SV for verification, does not cover the principles of UVM verification. I have asked AI about writing a testbench, it shows me that writing with module tb + interface + clocking block + class + mailbox/queue/event + assertion is a good way. And I would like to ask your practical industial experience about SV.:)
