Forum Discussion
New ContributorLibrary use with files with the same name
I have multiple modules with the same name and hence have assigned them to different design libraries using: assignments -> settings -> files -> properties
However during compilation I get the following error:
Error (10703): SystemVerilog error at main_project.sv(415): can't resolve aggregate expression in connection to port 18 on instance "my_module_i" because the instance has no module binding
I assume this means the compiler can't find that entity when it searches the design libraries. How can I get Quartus to look for that entity in the correct place?
main_project is in the default 'work' library and my_module.sv is library which I specified the name for. Both files are SystemV.
8 Replies
- RichardT_altera
Super Contributor
Hi, I found a workaround for the error you are seeing:
http://fpgaforum.blogspot.com/2017/07/quartus-ii-synthesis-error-during.html
Please try this and let me know if the error still exists?
ChrisF1Sorry that link doesn't help.
I have added all files to the design, however this has to do with the design libraries they are built into. Since two files (and the modules inside them) have the same name, they cannot be built into the same library. If they are, I get an error about duplicate entities. I can get around that error by building each one into different design libraries. The libraries are 'work' and 'my_lib'.
Therefore 'main_project' is in 'work' and 'my_module_i' is in 'my_lib'. When Quartus compiles 'main_project' it treats 'my_module' as if it doesn't exist - I assume it searches work, can't find it and gives up with the error no module binding.
In VHDL the solution would be to add library my_lib; refer to my_lib at the instantiation but this isn't possible in SysV.
sstrellCan you post some code and list file names? It might be easier to diagnose if you show what's involved.
