Library use with files with the same name

Question

I have multiple modules with the same name and hence have assigned them to different design libraries using: assignments -&gt; settings -&gt; files -&gt; properties
However during compilation I get the following error:
Error (10703): SystemVerilog error at main_project.sv(415): can't resolve aggregate expression in connection to port 18 on instance "my_module_i" because the instance has no module binding
I assume this means the compiler can't find that entity when it searches the design libraries. How can I get Quartus to look for that entity in the correct place?

main_project is in the default 'work' library and my_module.sv is library which I specified the name for. Both files are SystemV.

richardt_altera · Answer

Hi, I found a workaround for the error you are seeing: http://fpgaforum.blogspot.com/2017/07/quartus-ii-synthesis-error-during.htmlPlease try this and let me know if the error still exists?

chrisf1 · Answer

Sorry that link doesn't help.
I have added all files to the design, however this has to do with the design libraries they are built into. Since two files (and the modules inside them) have the same name, they cannot be built into the same library. If they are, I get an error about duplicate entities. I can get around that error by building each one into different design libraries. The libraries are 'work' and 'my_lib'.
Therefore 'main_project' is in 'work' and 'my_module_i' is in 'my_lib'. When Quartus compiles 'main_project' it treats 'my_module' as if it doesn't exist - I assume it searches work, can't find it and gives up with the error no module binding. 
In VHDL the solution would be to add library my_lib; refer to my_lib at the instantiation but this isn't possible in SysV.

sstrell · Answer

Can you post some code and list file names?  It might be easier to diagnose if you show what's involved.

chrisf1 · Answer

I have to limit code and file names protect IP. This is a large design with many files so it would get complicated to list everything anyway.

The simplest way of explaining the issue is: if a source file (.sv) is assigned to any design library, other than work, it cannot be seen by the Quartus compiler.
As shown below; if anything is in the box circled then Quartus doesn't know that file exists and gives an error.

This box is in: assignments -&gt; settings -&gt; files -&gt; properties

My question is, how do I tell Quartus to go and look in my_lib to find that design unit?

richardt_altera · Answer

Have you try to include design files libraries in your project?You may checkout 2.4.1. Including Design Libraries in the document below. 
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-qpp-getting-started.pdf
You may also checkout the 5.4.3. Ensure Distinct VHDL Namespace for Each Library. It could be one of the reason the Quartus could not find the file. Try to change to unique file name and check if you are able to solve the error.

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Library use with files with the same name

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