New Contributor
New ContributorSorry that link doesn't help.
I have added all files to the design, however this has to do with the design libraries they are built into. Since two files (and the modules inside them) have the same name, they cannot be built into the same library. If they are, I get an error about duplicate entities. I can get around that error by building each one into different design libraries. The libraries are 'work' and 'my_lib'.
Therefore 'main_project' is in 'work' and 'my_module_i' is in 'my_lib'. When Quartus compiles 'main_project' it treats 'my_module' as if it doesn't exist - I assume it searches work, can't find it and gives up with the error no module binding.
In VHDL the solution would be to add library my_lib; refer to my_lib at the instantiation but this isn't possible in SysV.
Super ContributorCan you post some code and list file names? It might be easier to diagnose if you show what's involved.
New ContributorI have to limit code and file names protect IP. This is a large design with many files so it would get complicated to list everything anyway.
The simplest way of explaining the issue is: if a source file (.sv) is assigned to any design library, other than work, it cannot be seen by the Quartus compiler.
As shown below; if anything is in the box circled then Quartus doesn't know that file exists and gives an error.
This box is in: assignments -> settings -> files -> properties
My question is, how do I tell Quartus to go and look in my_lib to find that design unit?
Super ContributorHave you try to include design files libraries in your project?
You may checkout 2.4.1. Including Design Libraries in the document below.
You may also checkout the 5.4.3. Ensure Distinct VHDL Namespace for Each Library. It could be one of the reason the Quartus could not find the file. Try to change to unique file name and check if you are able to solve the error.
New ContributorIf you have any more information than section 2.4.1 that would be great. I've tried various things there without success.
5.4.3 is the solution for VHDL but I am using System Verilog.
