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c-thaler's avatar
c-thaler
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

Library naming issue with "add_hdl_instance"

My static IP component needs a floating point "multiply and add". So I added an altera_fp_functions instance via "add_hdl_instance" in the elaboration function of my IP's TCL file.

That works fine so far. However, Platform Designer puts the component into a library with a generated name, which is based on the system's hierarchy (something like "top_myip_mymultiplyadd").
Of course, my IP component's VHDL code must be generic. It must not depend on any system hierarchy.

Is there a way to force Platform Designer to use a static library name?

4 Replies

    • c-thaler's avatar
      c-thaler
      Icon for Occasional Contributor rankOccasional Contributor
      4 years ago

      Thanks for the reply. I solved the issue in the meantime. But I did not follow the document you referred to.

      I added a Verilog wrapper file for the generated floating point instance, since Verilog does not have the concept of libraries. Then I added the wrapper file to qip into the same library my component uses. After that, I was able to successfully instantiate the Verilog wrapper from my component's source code. I did not use autogenerated names, so it worked without any regex substitutions to the original source code.

      • RichardT_altera's avatar
        RichardT_altera
        Icon for Super Contributor rankSuper Contributor
        4 years ago

        Good to know that you are able to found the solution. This will be helpful to those who may come across similar issue.

        With that, I will now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

        Best Regards,
        Richard Tan

        p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos.

    • JHill1's avatar
      JHill1
      Icon for Occasional Contributor rankOccasional Contributor
      8 months ago

      I had a quick look at what is being suggested as the TCL orchestrated solution above, see below.

      All I can say is that configuring IP with VHDL generics just might be a simpler and less kludgy way to integrate Intel/Altera generated IP into HDL?

      proc generate { entity_name } {
      # get the autogenerated name for emif_instance_name added
      # via add_hdl_instance
      set autogeneratedfixedname [get_instance_property \
      emif_instance_name HDLINSTANCE_GET_GENERATED_NAME]
      set fileID [open "generated_toplevel_component.v" r]
      set temp ""
      # read the contents of the file
      while {[eof $fileID] != 1} {
      gets $fileID lineInfo
      # replace the top level entity name with the name provided
      # during generation
      regsub -all "substitute_entity_name_here" $lineInfo \"${entity_name}" lineInfo
      # replace the autogenerated name for emif_instance_name added
      # via add_hdl_instance
      regsub -all "substitute_autogenerated_emifinstancename_here" \
      $lineInfo"${autogeneratedfixedname}" lineInfo \
      append temp "${lineInfo}\n"
      }