New Contributorleft bound (21) fo slice must belong to range & formal port or parameter must have actual or default value
I have two errors. "left bound (21) of slice must belong to range (18 downto 0) of corresponding object" and "formal port of parameter "x_i" must have actual or default value".
How can I fix it?
Here is a code
----Booth_multi----
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Booth_multi is
port ( a : in std_logic_vector(15 downto 0); -- 16비트의 입력 a
b : in std_logic_vector(15 downto 0); -- 16비트의 입력 b
p : out std_logic_vector(31 downto 0)); -- 32비트의 출력 p
end Booth_multi;
architecture behavior of Booth_multi is
component booth_unit
Port ( P : in std_logic_vector(15 downto 0);
Y : in std_logic_vector(15 downto 0);
x_i : in std_logic_vector(3 downto 0);
Z : out std_logic_vector(2 downto 0);
P_n : out std_logic_vector(15 downto 0));
end component;
type conections is array (0 to 7) of std_logic_vector (15 downto 0);
Signal wires: conections;
Signal eX: std_logic_vector (18 downto 0);
constant bitsCalc : integer := (3-(16 mod 3)) mod 3; -- bit 계산
begin
eX <= a(15) & a(15) & a & '0'; --ex는 a(15)a(15)a0이 된다.
wires(0) <= (others => '0');
iter: for i in 0 to 7 generate
mult: booth_unit port map (P => wires(i), Y => b, x_i => eX(3*i+3 downto 3*i),
Z => p(3*i+2 downto 3*i), P_n => wires(i+1) ); -- booth_unit 포트를 연결
end generate;
p(31 downto 16+bitsCalc) <= wires(6)(16-bitsCalc-1 downto 0);
end behavior;
-----Booth_unit----
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.std_logic_arith.ALL;
use ieee.std_logic_unsigned.ALL;
entity Booth_unit is
Port ( P : in std_logic_vector(15 downto 0);
Y : in std_logic_vector(15 downto 0);
x_i : in std_logic_vector(3 downto 0);
Z : out std_logic_vector(2 downto 0);
P_n : out std_logic_vector(15 downto 0)
);
end Booth_unit;
architecture behavior of Booth_unit is
signal S, Long_P, Long_Y, Long_Y_2 , Long_Y_3, Long_Y_4: std_logic_vector(18 downto 0);
begin
Long_P <= P(15) & P(15) & P(15) & P;
Long_Y <= Y(15) & Y(15) & Y(15) & Y;
Long_Y_2 <= Y(15) & Y(15) & Y & '0';
Long_Y_3 <= Long_Y + Long_Y_2;
Long_Y_4 <= Y(15) & Y & "00";
the_mux: process(x_i,Long_P, Long_Y, Long_Y_2, Long_Y_3, Long_Y_4)
begin
case x_i is
when "0000" => S <= Long_P;
when "0001" => S <= Long_P + Long_Y;
when "0010" => S <= Long_P + Long_Y;
when "0011" => S <= Long_P + Long_Y_2;
when "0100" => S <= Long_P + Long_Y_2;
when "0101" => S <= Long_P + Long_Y_3;
when "0110" => S <= Long_P + Long_Y_3;
when "0111" => S <= Long_P + Long_Y_4;
when "1000" => S <= Long_P - Long_Y_4;
when "1001" => S <= Long_P - Long_Y_3;
when "1010" => S <= Long_P - Long_Y_3;
when "1011" => S <= Long_P - Long_Y_2;
when "1100" => S <= Long_P - Long_Y_2;
when "1101" => S <= Long_P - Long_Y;
when "1110" => S <= Long_P - Long_Y;
when "1111" => S <= Long_P;
when others => NULL;
end case;
end process;
P_n <= S(18 downto 3);
Z <= S(2 downto 0);
end behavior;
