left bound (21) fo slice must belong to range & formal port or parameter must have actual or default value

You are exceeding the allowed range for x_i. It is defined as

Signal eX: std_logic_vector (18 downto 0);

, but later on, you attempt to iterate across it like this:

 iter: for i in 0 to 7 generate
    mult : booth_unit
        port map
        (
            P => wires(i),
            Y => b, 
            x_i => eX(3*i+3 downto 3*i), 
            Z => p(3*i+2 downto 3*i), 
            P_n => wires(i+1)
        ); -- booth_unit
 end generate;

Note: you are iterating i from 0 to 7, but 3 * 6 + 3 is already exceeding the bounds of the vector. No idea what you are trying to do, but the loop should probably go from 0 to 5 only...

The second error is most likely only a consequence of the first.