Latches in Compilation Report

I am no expert, but for me it always displays that information in the processing messages during compilation. It will give a warning stating that it is inferring a latch for a specific signal.

Latches are easy to get rid of as long as you provide a default case for all signals.

Look in the Analysis & Synthesis report under "Optimization Results --> Register Statistics".

This section of the Analysis & Synthesis report has a table of combinational feedback loops that synthesis recognized as latches and implemented with a latch representation internal to Quartus. This table, called "User-Specified and Inferred Latches", indicates whether each latch has an implementation that is at risk of timing hazards like glitches. Even if all latches are marked as free of timing hazards, it is recommended to avoid them in your design unless they are used for something where neither setup nor hold timing matters (like latching data off a processor bus with the data not changing during the time the latch outputs are being used). The timing analysis of latches is approximate, and you probably got a warning about that in the timing analyzer if you have combinational feedback loops in the design.

This section of the Analysis & Synthesis report has another table of combinational loops that were not implemented with the internal latch representation. This table is called "Logic Cells Representing Combinational Loops". All loops in this table could be trouble.

These tables are produced only when needed. If you have no combinational loops at all, you won't get either table.

I have been searching for a meaningful explanation of the warning message "Warning: Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family". I was not sure whether or not it meant that I actually had latches in my design, or if it was just a generic warning.

Thanks to Brad, I at least know where to check for latches in the synthesized output.