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Altera_Forum's avatar
Altera_Forum
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17 years ago

Latches in Compilation Report

Hi, I am currently experiencing some timing issues in my design, and I suspect it might be due to inferred latches. Therefore, I would like some way of checking the compilation report to see i...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

I am no expert, but for me it always displays that information in the processing messages during compilation. It will give a warning stating that it is inferring a latch for a specific signal.

Latches are easy to get rid of as long as you provide a default case for all signals.