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Altera_Forum's avatar
Altera_Forum
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17 years ago

Latches in Compilation Report

Hi, I am currently experiencing some timing issues in my design, and I suspect it might be due to inferred latches. Therefore, I would like some way of checking the compilation report to see i...
Altera_Forum's avatar
Altera_Forum
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16 years ago

I have been searching for a meaningful explanation of the warning message "Warning: Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family". I was not sure whether or not it meant that I actually had latches in my design, or if it was just a generic warning.

Thanks to Brad, I at least know where to check for latches in the synthesized output.