Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

large divider VHDL

hi, i have to perform a division 112 bit dividend and 112 bit divisor.

To enhance precision (fractional), i shift the numerator by 6 to the left.

To perform this huge division, i perform multiple subtraction until numerator is positive.

if (numerator positive)

Numerator <= Numerator - Denominator

Quotient <= quotient +1;

when i check for timing, the subtractor path is the most critical, i think because of the bus size.

How can i speed this task?

Numerator and denominator don't change every clock cycle, so i could use a multicycle. How i use this?

I would use lpm_add_sub to pipeline the subtractor, i have quartus 12 and this is not present in the megawizard. How i can instantiate in my vhdl?

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    i have a lot of time for division so is not an efficienty problem,

    the problem, like in your approach, is that i have a 112 dividend and divisor and the substraction is slow.

    i tried to do a multicycle

    when en = 1 i do dividend - divisor

    when en = 0 i do nothing

    en change at half rate

    these are the constraint

    # Setup multicycle of 2 to enabled driven destination registers

    set_multicycle_path 2 -to [get_fanouts [get_pins enable_reg|q*]

    -through [get_pins -hierarchical *|*ena*]] -end -setup#Hold multicycle of 1 to enabled driven destination registers

    set_multicycle_path 1 -to [get_fanouts [get_pins enable_reg|q*]

    -through [get_pins -hierarchical *|*ena*]] -end –hold
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    I understand your point. You tried to add a clk enable. It's like a pipeline. One time a did a similar huge vector and didn't improve the speed. Try improve the design slow down the clk_en signal. One tick per 10 clocks, for example.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    yes with clock enable i can meet setup constraints, i found a core on opencores that makes division like you said before, much faster