large divider VHDL

i have a lot of time for division so is not an efficienty problem,

the problem, like in your approach, is that i have a 112 dividend and divisor and the substraction is slow.

i tried to do a multicycle

when en = 1 i do dividend - divisor

when en = 0 i do nothing

en change at half rate

these are the constraint

# Setup multicycle of 2 to enabled driven destination registers

set_multicycle_path 2 -to [get_fanouts [get_pins enable_reg|q*]

-through [get_pins -hierarchical *|*ena*]] -end -setup#Hold multicycle of 1 to enabled driven destination registers

set_multicycle_path 1 -to [get_fanouts [get_pins enable_reg|q*]

-through [get_pins -hierarchical *|*ena*]] -end –hold