Large clock skew

IO ports generally have clock skew. The clock delay inside the FPGA to the latch register is some real delay(input buffer -> clock tree, etc.) and probably 4.514ns. The external register that launches the data has a 0ns clock delay. So all clock delay inside the FPGA shows up as skew(unlike internal paths, that have clock delay to both launch and latch registers which generally cancels out). So this pretty normal. If it's failing timing because of this clock skew, add a PLL if there isn't one, phase-shift the PLL back(or do a positive phase-shift and multicycle of 2, which is the same thing) or take it off a global.

(And note that it's not like the external device doesn't have clock skew. It's just more common it's hidden. For example, the external device might have a Tco max of 6ns, which under the hood might be a clock skew of 3.5ns and register to output of 2.5ns, but the whole thing is just listed as 6ns and put into the set_input_delay -max value.)