jk flip flop usin dataflow model

How to design jk flip flop using dataflow model.

When i run the code it shows an error "iteration limit reached".

my vhdl code is

library ieee;

use ieee.std_logic_1164.all;

-------------------------------------------------------------

entity jkff_dataflow is

port(j,k,clk,rst:in std_logic;

q,qbar:inout std_logic);

end jkff_dataflow;

-------------------------------------------------------------

architecture jkff_dataflow of jkff_dataflow is

begin

q<=(((k and clk) and qbar) nor qbar) nor rst;

qbar<=((j and clk) and q) nor q;

end jkff_dataflow;