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Honored Contributor
Honored Contributorjk flip flop usin dataflow model
How to design jk flip flop using dataflow model. When i run the code it shows an error "iteration limit reached". my vhdl code is library ieee; use ieee.std_logic_1164.all; -----...
Altera_ForumHonored Contributor
Honored ContributorIn don't know what this data flow model is you're talking about. Vhdl describes a logic circuit, hence it can only be a behaviour. Your code just describes a logic loop.
