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Altera_Forum
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10 years ago

jk flip flop usin dataflow model

How to design jk flip flop using dataflow model. When i run the code it shows an error "iteration limit reached". my vhdl code is library ieee; use ieee.std_logic_1164.all; -----...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

In don't know what this data flow model is you're talking about. Vhdl describes a logic circuit, hence it can only be a behaviour. Your code just describes a logic loop.