Issue with Quartus Prime PRO for Stratix 10 when using a string type in a VHDL project.

Dear KhaiY, Thank you for your message and for remembering my problem.. but I'm not ready yet. :-( I am very sorry about this delay. I have so many different problems lately. I tried to prepare a code showing the issue but I didn't have enough time. We have the end of the semester here at the university and I have hundreds of students to whom I have to give grades. And because of coronavirus it is a crazy time. I'll prepare the code as soon as possible. As to the issue: Solving this Stratix_10 problem in Quartus Prime Pro is very important to me. In general, I think the problem appears when sharing string data between different entities. I need to prepare a short code showing this problem, but as I told you before, each compilation of the simplest code for Stratix_10 that I try to test takes me at least 9 minutes! which means: only seven tries take about an hour. This is not the case with another family of FPGAs (MAX10, Cyclon_IV and others). I promise that I'll do my best to prepare the code showing the issue as soon as possible. It is important for me because without your help in solving this problem, I can't and I won't be able to use my own IPs codes for the Stratix_10 chips. :-( Best Regards, (jd)