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bitstreamer's avatar
bitstreamer
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

Issue with compiling core libraries / Methodology for reliably exporting a design to a high end external simulator like Questa Ultra

When creating a large design, we have higher end simulators. I'd like to simulate the design in an external environment.

I have built a compile_all tcl script, which executes in the external environment correctly - zero compile errors.

However, when I optimize, I get a lot of 'module not found' errors, mainly due to core libraries that are usually pre-compiled when simulating within Quartus.

How do I export these core libraries for compilation, specifically to Questa Advanced Simulator? Further, is there

I've already tried the EDA export dialog, it doesn't handle these libraries.

With other FPGA companies, this is a one step process, is there a defined methodology for exporting to external advanced simulators?

9 Replies

  • RichardT_altera's avatar
    RichardT_altera
    Icon for Super Contributor rankSuper Contributor
    6 years ago

    Unfortunately, the EDA export dialog does not export the library files.

    Can you try to invoke the external simulator, (probably the same with Modelsim), go to File > New > Library. And choose to Create a map to an existing library.

    Let me know whether it helps.

  • bitstreamer's avatar
    bitstreamer
    Icon for Occasional Contributor rankOccasional Contributor
    6 years ago

    The problem I'm having is that I don't know where the libraries are, otherwise I could map them. Do I need to build them somehow?

  • bitstreamer's avatar
    bitstreamer
    Icon for Occasional Contributor rankOccasional Contributor
    6 years ago

    Just so I understand - one of the errors I'm getting in optimization is functions like oper_add, which is located in

    /home/tools/intel/FPGA/18.1/quartus/eda/sim_lib/sgate.vhd:ENTITY oper_add IS

    What is the strategy for building - is there a modelsim.ini for this sim_lib directory, or should I brute force a .do file to compile each file individually? I'd like this to scale, so I'd like to make sure I understand the methodology Intel has in mind.

    So am I correct that I should vcom vhdl files into work, and vlog verilog files into work from that directory? I would assume that operation such as oper_add would be in a library that is referenced by a library definition at the top of the design file that uses oper_add.

    • bitstreamer's avatar
      bitstreamer
      Icon for Occasional Contributor rankOccasional Contributor
      6 years ago

      Hi Richard, replied to your message, I'm available anytime this week.

  • bitstreamer's avatar
    bitstreamer
    Icon for Occasional Contributor rankOccasional Contributor
    6 years ago

    Richard, thank you for the help, it's becoming clearer, but it's not complete. I'm an Intel partner, would it be useful for us to create a github export for quartus once we have all the libraries identified?

    For instance, altera_pll isn't covered, I'm resolving these dependencies manually through the sim_lib directory as shown below. Is there another methodology somewhere that I'm missing?

    > vopt <commands>

    ** Error: <filepath>(66): Module 'altera_pll' is not defined.

    >find <command>

    FPGA/18.1/quartus/eda/sim_lib/altera_lnsim.sv:module altera_pll

  • bitstreamer's avatar
    bitstreamer
    Icon for Occasional Contributor rankOccasional Contributor
    6 years ago

    Hi Shyan -

    Not sure you are getting my emails past week or so. I'm in the meeting now, it's 10:04 Pacific, 1:04 eastern. I can meet tonight at 10pm eastern (my time). My understanding is that would be 10am your time. I would guess right now it's 1am your time!

    I can work late hours, give me the time in Malaysia time that you can meet, and we can knock this out!