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bitstreamer's avatar
bitstreamer
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6 years ago

Issue with compiling core libraries / Methodology for reliably exporting a design to a high end external simulator like Questa Ultra

When creating a large design, we have higher end simulators. I'd like to simulate the design in an external environment. I have built a compile_all tcl script, which executes in the external environ...
bitstreamer's avatar
bitstreamer
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

Just so I understand - one of the errors I'm getting in optimization is functions like oper_add, which is located in

/home/tools/intel/FPGA/18.1/quartus/eda/sim_lib/sgate.vhd:ENTITY oper_add IS

What is the strategy for building - is there a modelsim.ini for this sim_lib directory, or should I brute force a .do file to compile each file individually? I'd like this to scale, so I'd like to make sure I understand the methodology Intel has in mind.

So am I correct that I should vcom vhdl files into work, and vlog verilog files into work from that directory? I would assume that operation such as oper_add would be in a library that is referenced by a library definition at the top of the design file that uses oper_add.