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Honored ContributorISP 1761 VHDL USB Peripheral Controller Timing Issues
Hi Altera Forum Members,
I am currently Designing on the Terasic DE4 with a Stratix IV EP4SGX230 and Quartus 12.1SP1(formerly just 12.1) for my Master Thesis. I have no experience with the Nios II and am kind of a purist, so I wanted to write a VHDL Controller Core for using the ISP1761 as USB Peripheral. The Chip Controller has got 3 entitys. One HAL managing the Timing specifications, a Configuration Controller, Configuring the ISP1761 as Peripheral and a "worker", which handles interrupts, Descriptor Requests/USB Requests and Incoming/Outgoing Data on the EP1 Bulk Endpoint. I got to the point, that everything, beginning at USB Bus Enumration and Sending of Data worked flawless. Then I added some more entitys. The ISP Core (which runs at 50 MHz) is connected to a Communication Controller (running at 200MHz because interfacing to the DDR-Ram is planned) which implements a custom protocoll of commands, via two DCFIFO's. Sometimes the ISP Core Works, but at some point, when i change some code in any entity the Design suddenly doesn't get through usb bus enumeration, waiting forever for the interrupt, that tells the controller, the Descriptor has been transmitted. Even if I change something in the Communication Controller it can happen, that the ISP Core suddenly doesn't work anymore. I am struggling for about two months with this issue, sometimes it works, sometimes not. The behaviour is, in a way nondeterministic. So I assume, that this has something to do with the Timing Constraints, and that the Fitter Places the entity to another location, when something in the design changes. I tried it with a Logic Lock on the ISP Core, which worked fine for a while, but at some point it all crashed again. Because the communication with the ISP is somewhat asynchronous, I tried to constrain my design, following this post: alteraforums.net/forum/showthread.php?t=24810 but had no luck with that. Following the Data Sheet (shop.in-circuit.de/data/datasheet/ISP1761.pdf ,page 142 - Peripheral PIO Timing), I had the following constraints:
create_clock -name GCLKIN -period 10.0 # base clock
derive_pll_clocks
derive_clock_uncertainty
create_generated_clock -name OTG_WE_n_CLK -source }]
create_generated_clock -name OTG_OE_n_CLK -source }]
# positive edge of OTG_WE_n is the same edge, that triggers sampling of the DATA line -> multicycle to 0
set_multicycle_path -hold -to 0# data has to hold 2 ns after WR_N HIGH
set_output_delay -clock OTG_WE_n_CLK -min -2.5 ]# CS_N has to hold 1 ns after WR_N HIGH
set_output_delay -clock OTG_WE_n_CLK -min -1.5
# input delay from RD_n to output of DATA from USB (multicycle set to 2, since 50MHz clk)
set_multicycle_path -from {OTG_D
} -to {ISP1761Control_INST|isp_hal|hal_out.DAT
} 2
set_input_delay -clock OTG_OE_n_CLK -max 33.0 ]
# false paths for peripheral (such as buttons, leds etc.)
set_false_path -to }]
set_false_path -to }]
set_false_path -to }]
set_false_path -to
set_false_path -to
set_false_path -from }]
set_false_path -from }]
set_false_path -from
set_false_path -to
