ISP 1761 VHDL USB Peripheral Controller Timing Issues

Thanks for the hint rbugalho. In fact, I did just that earlier in the design process. But that didn't work. In my HAL entity I have this:

OTG_OE_n        <= usb_read_n;
OTG_WE_n       <= usb_write_n;
OTG_D              <= usb_d_in when (usb_write_n = '0' and usb_read_n = '1') else (others => 'Z');
usb_d_out          <= OTG_D;

usb_read_n and usb_read_n as internal signals, so I don't have to declare OTG_OE_n and OTG_WE_n as buffers (at my working group they say this is bad design practice) to get the tristate working. When I set OTG_WE_n and OTG_OE_n as the targets, TimeQuest says I have unconstrained Clocks:

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Node: ISP1761Control:ISP1761Control_INST|ISP1761HAL:isp_hal|usb_write_n was determined to be a clock but was found without an associated clock assignment.

Node: ISP1761Control:ISP1761Control_INST|ISP1761HAL:isp_hal|usb_read_n was determined to be a clock but was found without an associated clock assignment.

No paths exist between clock target "OTG_WE_n" of clock "OTG_WE_n_CLK" and its clock source. Assuming zero source clock latency.

No paths exist between clock target "OTG_OE_n" of clock "OTG_OE_n_CLK" and its clock source. Assuming zero source clock latency.

--- Quote End ---

When I hit "Report Unconstrained Paths" usb_write_n and usb_read_n are listed as unconstrained Base Clocks, since they are feeding OTG_OE_n and OTG_WE_n.

I assume the "Assuming zero source clock latency" is not so good for analysing the timing :)